This application relates, in general, to buffer circuits and, more particularly, to low power, high speed buffer circuits for use, for example, in integrated circuit logic devices.
As the technology for producing large scale integration devices advances, logic designers who design devices such as microprocessors and microcomputers, have the capability of producing integrated circuit chips having ever increasing numbers of active devices such as MOS field effect transistors on a single piece of silicon. The increased number of devices on a chip is accomplished in part by reduction of device geometries so that the devices themselves are smaller. Large scale logic circuits must operate at relatively high speed to be economic and useful. High speed may be obtained by a number of methods, and having smaller device geometries contributes to high speed operation. High speed operation usually also implies, however, relatively high power consumption.
As more and more devices are fabricated on a single integrated circuit chip operating at high speed, power consumption requirements and power dissipation requirements become extremely important.
Accordingly, it is an object of the present invention to provide a buffer circuit used with microprocessors which is capable of fast response and high speed operation but yet dissipates substantially less power than previously used devices.
Another object of the present invention is to provide a clocked driver circuit which is high speed and consumes a low amount of power and is useful in a buffer circuit.